Generally, programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs), include thousands of programmable logic cells that perform logic operations. For example, each such logic element (“LE”) may include a look-up table (“LUT”), a register, and a small amount of other circuitry. The LUT may be programmable to produce an output signal that is any logical combination or function of the inputs to the LUT. The LE may be programmable with respect to whether and how the register is used, and what control signals (e.g., clock, clock enable, clear, etc.) are selected for application to the register. In addition to the LEs, an FPGA typically includes programmable interconnection circuitry for conveying signals to, from, and/or between the LEs in any of many different ways. This allows the relatively simple logic capabilities of individual LEs to be concatenated to perform logic tasks of considerable complexity.
It has become increasingly standard in FPGA architectures to add dedicated or “hard” blocks to programmable logic to add common functionality to the FPGA. These functional blocks incorporate specialized logic devices adapted to specific logic operations, such as serializers, deserializers, filters, adders, multiply and accumulate (MAC) circuits, and phase-locked loops (PLL). The logic cells and functional blocks are interconnected by a configurable interconnect network. The configurable interconnect network selectively routes connections between and among the logic cells and functional blocks. By configuring the combination of logic cells, functional blocks, and the interconnect network, a programmable device can be adapted to perform virtually any type of information processing function. Specialized blocks that are added to an FPGA may decrease the size of a function or to improve performance of a speed-critical block. A further attraction of specialized blocks is that the fixed implementation provides the benefit of a consistent implementation, reducing the effort of timing closure.
One of the main properties of specialized blocks is that they tend to provide dramatic benefits when used. However, it is rare that all the specialized blocks are used and sometimes specialized blocks are not used at all. Some of the major hurdles in adding specialized blocks to FPGAs are that 1) specialized blocks are a great advantage for some users, but may sometimes be wasted area for other users, and 2) it is not cost-efficient to make a family of FPGAs with too many different members and variations, and often it is not known until long after the device is defined which specialized blocks should be included in a design.